1. Field of the Invention
This invention relates to the field of multiplexers operable in time divisions to transmit sampled data from a plurality of parallel input channels on a serial signal line, and to recover the parallel data from the serial signal line. More particularly, the invention relates to such a multiplexer and demultiplexer wherein means are provided to check the recovered data and to re-synchronize the channels such that the respective parallel inputs and outputs always correspond correctly. In the event of disturbance, the sequence of outputs is automatically corrected, without the need to employ framing or stop bits to precede or space frames of sampled data.
2. Prior Art
A variety of digital multiplexers are known wherein parallel input channels are sampled and the content of each sampled channel is placed in turn on a serial output during a time division corresponding to that channel. For example, a counter at the input end repetitively cycles through the channels in order. Gates responsive to the clock are operable for gating the signal on each channel through to the serial signal line during its respective time division. The data is recovered at a receive end by an apparatus operating in the reverse, that is by dividing the serial stream into the individual samples and routing the samples in turn to respective parallel output channels. One pass through all the channels is called a frame. Typically, extra transmitted bits or a time lapse are inserted to mark the start and/or stop of a frame.
According to some data transmission techniques, the clock used for de-multiplexing serial data can be derived directly from the data itself. Notwithstanding expected variations in data, over time a phase-locked loop control can derive the sampling clock from the sampled data. While systems of this type are reasonably effective at serializing the parallel data and converting the received serial transmission back into parallel channels, it sometimes happens that the proper order of channels becomes disturbed. Known time division multiplexers synchronize the input and output channels based on the framing or synchronization bits preceding or following the frame.
Additional framing procedures and codes such as inserted gaps, start/stop characters and the like, use time that could be employed for higher frequency sampling and better multiplexing effectiveness. The framing bits or characters are normally inserted and detected using additional circuitry that increases the expense of the multiplexer and reduces the efficiency of the overall device. The present invention avoids the need for extra time devoted to start/stop signalling. A synchronizing marker is added directly over the data for at least one given channel to be used as a marked or synchronizing channel. The marker is arranged as an "impossible" data pattern and during multiplexing the marker is inserted over a predetermined data pattern on the given channel. At the demultiplexing end the marker pattern is detected and the correct pattern replaced, provided the marker was found in the data for the given channel. Otherwise the sequence of channel demultiplexing is reset. This technique does not require that a gap be opened or that available time divisions be devoted to transmission of extra framing characters.
The invention takes advantage of the fact that the multiplexer samples incoming data streams at a rate substantially higher than the frequency at which digital levels change in the data. Where the sampling rate is higher than the rate of change of the data, a group of unchanged bits are transmitted during successive samples for a given input channel. According to the invention, when a predetermined succession of bits is detected during successive samples on a specific channel to be used as a marked channel, for example three unchanged ones in the binary stream, the middle bit is inverted. This impossible data pattern 1-0-1 becomes a marker for that channel. Should the inverted bit be detected in a channel other than the marked one, then the receiver section of the multiplexer/demultiplexer can be reset to re-synchronize the parallel inputs to the parallel outputs, whereupon correct operation resumes.
It is known in the art to insert supervisory signalling or framing bits in extra time slots made available therefor in a digital signal. Reference can be made, for example, to U.S. Pat. Nos. 3,936,609-Waldeck (inserts alarm bits); 3,748,393-Baxter (use extra bit spaces for signalling); 3,873,776-Smith, Jr. et al (insert alarm pulse). These patents use available time which could be used for data transmission, or require extra circuitry to detect when time is available, perhaps compressing the data, and then to insert signalling codes.
It is also known in the art to employ a particular code as a start or stop signal. In U.S. Pat. No. 4,243,930-DeCoursey, for example, three successive zero bits are used to define a time space between frames, for synchronizing the output and the input. Other examples along these lines can be found in U.S. Pat. Nos. 4,538,386-McNesby et al; 3,970,799-Colton et al, and in other disclosures. These also require that time be devoted to the start/stop codes. General purpose bit sampling multiplexers can be found, for example in U.S. Pat. Nos. 3,840,705-Haskett et al and 4,310,922-Lichtenberger.
In U.S. Pat. No. 3,995,120-Pachynski, Jr., the idea is disclosed that where the sampling rate is much higher than the average rate of data change, it is possible to compress the data and thereby open up additional time for signalling. Where the data rate is slower than the sampling rate, Pachynski bunches together samples, leaving a time space before and after the frame of active data channels, for use as signalling and/or framing bits.
Each of the foregoing prior art disclosures has means to accomplish multiplexing and means to retain the proper order of the channels when demultiplexing. However, all do so in ways that require substantial additional circuitry and/or take up time for framing or synchronizing signals. The present invention on the other hand puts a signalling bit directly into the data, the data being represented by a plurality of samples at the higher sampling rate. The signalling bits need not use up time divisions and need not appear during every transmitted frame. Each time the predetermined pattern (e.g., a string of unchanged high levels) appears in the successive samples for the marking one of the parallel inputs, a central bit is inverted and used as a marker for this one channel. Preferably, the mark channel is the channel transmitted at the beginning of a frame of sampled channels. Accordingly, whenever the marker bit is detected, the counter or the like that advances the demultiplexer through the respective channels when converting the data from serial to parallel can be simply reset.
The invention is advantageously embodied as a two channel multiplexer. In this event, the means cycling through the input channels (i.e., the two parallel inputs) can be as simple as a flip flop. In a device in which a large number of channels are used, a counter and a one-of-n decoder can provide sequencing to gate through samples of the parallel inputs to the serial bit stream. Preferably, additional flip flops defining an input shift register are provided such that the successive samples for a particular channel, i.e. the synchronizing channel, are stored and compared to a predetermined pattern arranged for insertion of a marker bit. The invention accomplishes synchronization automatically and with minimum of overhead and complexity.